The remaining output is. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. It has more speed performance at. OE does not affect the internal operations of the latches. It is ideal for 1. While the latch-enable LE input is high, the Q outputs follow the data D inputs.
Production processing does not necessarily include.
Подробности файла 74LVC573
Output Disable Time 1. Input voltage range, V. This is a individually operated, non profit site. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. When LE is taken low, the Q outputs are latched at the logic.
Inputs Accept Voltages to 5. One input at VCC — 0. These 8 bit D-Type latch are controlled by a latch.
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When a high logic level is dxtasheet to the output control input, all. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltage range applied to any output in the high or low state, V. While the LE inputs is held at a high level, the Q. Octal D-type Transparent Latches with 3-state Outputs.
Hold time, data after LE.
Pulse duration, LE high. Low voltage and high-speed operation is suitable at the battery drive product note type personal computer and low power consumption extends the life of a battery for long time operation. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.
Dynamic Low Level Quiet. The device is fully specified for partial power down applications using I OFF. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. In the high- impedance state, the outputs neither load nor drive the bus lines significantly. Functional operation under these conditions is.
Old data can be retained or new data can be entered while the outputs are in the high-impedance state. No purposely added lead.
This applies in the disabled state only. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. These devices are fully specified for partial-power-down applications using I. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Voltage range applied to any output in the high-impedance or dataaheet state, V. These devices feature inputs and outputs on opposite sides of the. It is ideal for 1. Output clamp current, I. A buffered output-enable OE input can be used to place the eight outputs in either a normal logic state high or low logic levels or the high-impedance state.
Output Voltage High or Low State. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The device is designed for operation with a power supply range of 1.